As the performance of an electronic device (e.g., a mobile device, a smart phone, etc.) is dramatically developed, the data processing speed of the electronic device is also becoming faster. However, an increase of the data processing speed may often cause an increase of power consumption in the electronic device. Therefore, an efficient management of power consumption is becoming a major issue in the electronic device.
A system-on-chip (“SoC”, also simply referred to as a “chip” hereinafter) is one of modules mounted in the electronic device. Recently, in order to reduce power consumption by varying the voltage and operating frequency applied to the chip according to the operating environment of the electronic device, a dynamic voltage and frequency scaling (DVFS) technology is applied to the SoC.
In order to improve the manufacturing yield, the modules such as the SoC may use an adaptive supply voltage (ASV) technique for controlling a supply voltage to the chip by measuring an actual operating speed and power consumption in the chip. A vendor which manufactures the chip may allow the chip to have a margin of operating at a voltage lower than the voltage defined in the specification so as to ensure the operating speed of the chip belonging to the same ASV group. However, when the chip is actually applied to the electronic device, the margin may be often different from that measured when the chip is manufactured, due to an inherent voltage drop of a board itself (also referred to as a board IR drop) and a power management integrated circuit (PMIC) variation. Because of this difference, the chip mounted in the electronic device may have a large voltage margin, which may inhibit an efficient power management in the electronic device. Or, due to such a difference, the chip mounted in the electronic device may have an insufficient voltage margin, which may cause defects in the manufacturing process of the electronic device.